1. Field of the Invention
The present invention relates to a semiconductor device and a process of production of the same, more particularly a semiconductor device which prevents autodoping of an impurity from an insulating film to a conductive layer, especially to a polysilicon layer, to suppress fluctuations in characteristics and a process of production of the same.
2. Description of the Related Art
Various bipolar transistors, capacitors, or resistors are structured with a conductive layer comprised of for example polysilicon formed on a semiconductor substrate and with interconnections formed on them via an insulating film.
FIGS. 1 to 4 show examples of cross-sectional structures of these elements. Each element shown in FIGS. 1 to 4 is formed on a p-type semiconductor substrate 1 and an n-type epitaxial layer 2 formed on the substrate 1. In all the elements of FIGS. 1 to 4, a LOCOS 3 for separating elements is formed on the surface of the n-type epitaxial layer 2. Below the LOCOS 3 is formed an element separating diffusion layer 4. The element separating diffusion layer 4 reaches the p-type semiconductor substrate.
FIG. 1 shows a vertical npn transistor (below, referred to as an “V-npn”), while FIG. 2A shows a lateral pnp transistor (below, referred to as an “L-pnp”)
FIG. 2B and FIG. 3A both show vertical pnp transistors. FIG. 2B shows a vertical pnp transistor comprising an n-type buried layer which separates electrically a p-type collector layer and the p-type semiconductor substrate. This is referred to as a “V-pnp” below. On the other hand, FIG. 3A shows a vertical pnp transistor wherein a p-type collector layer is formed to reach a p-type semiconductor substrate (substrate pnp). This is referred to as an “S-pnp” below.
FIG. 3B shows a capacitor of a metal-insulator-semiconductor (MIS) structure (below, referred to as an “MIS-C”), while FIG. 4 shows a polysilicon resistor (below, referred to as a “Poly-R”).
Below, the structure of each element mentioned above will be explained.
The V-npn of FIG. 1 has an n-type collector buried layer 5 at the surface layer of the p-type. semiconductor substrate 1. The n-type epitaxial layer 2 above it is made an n-type collector layer. At the surface layer of the n-type epitaxial layer 2 comprised of the n-type collector layer is formed a p-type base region 6. Around the p-type base region 6 is formed a graft base 6a. At the surface layer of the p-type base region 6 is formed an n-type emitter region 7. Also, at the n-type epitaxial layer 2 is formed a collector plug region (n+ sinker) 8 which connects to the n-type collector buried layer 5.
On the n-type epitaxial layer 2 or the LOCOS 3 is formed for example a silicon oxide film 9 as a first insulating film. The silicon oxide film 9 on the p-type base region 6 is provided with an opening. In the opening and on the silicon oxide film 9 around the opening is formed a first polysilicon layer (p-type base electrode 10) which is connected to the p-type base region 6 and serves as a base take-out part. The p-type base electrode 10 on the n-type emitter region 7 is provided with an opening.
On the p-type base electrode 10 or the silicon oxide film 9 is formed for example a silicon oxide film 11 as a second insulating film. The silicon oxide film 11 on the n-type emitter region 7 is provided with an opening. In the opening and on the silicon oxide film 11 around the opening is formed an n-type emitter polysilicon layer 12. The n-type emitter polysilicon layer 12 connects to the n-type emitter region 7 and serves as an emitter take-out part.
On a part of the p-type base electrode 10, on the n-type emitter polysilicon 12 and on the collector plug region 8 are formed electrodes 13.
Next, as shown in FIG. 2A, the L-pnp has an n-type base buried layer 14 at the surface layer of the p-type semiconductor substrate. The n-type epitaxial layer 2 on the n-type base buried layer 14 becomes an n-type base layer. At the surface layer of the n-type epitaxial layer comprised of the n-type base layer are formed a p-type emitter region 15 and a p-type collector region 16 separate from each other. Also, in the n-type epitaxial layer 2 is formed a base plug region (n+ sinker) 17 connected to the n-type base buried layer 14.
On the n-type epitaxial layer 2 or the LOCOS 3 is formed for example a silicon oxide film 9 as a first insulating film. The silicon oxide film 9 on the p-type emitter region 15 and the p-type collector region 16 are provided with openings. At the opening on the p-type emitter region 15 is formed an emitter take-out electrode 18 comprised of a p-type polysilicon layer. In the same way, at the opening on the p-type collector region 16 is formed a collector take-out electrode 19 comprised of a p-type polysilicon layer.
Electrodes 13 are formed on each of the emitter take-out electrode 18, collector take-out electrode 19, and base plug region 17.
As shown in FIG. 2B, the V-pnp has an n-type buried layer 20 at the surface layer of the p-type semiconductor substrate 1 on which a p-well comprised of a p-type collector region 21 is formed. Due to the n-type buried layer 20, the p-type collector region 21 and the p-type semiconductor substrate 1 are separated electrically. At the surface layer of the p-type collector region 21 are formed an n-type base region 22 and a graft base 22a connected to the base region 22. At the surface layer of the n-type base region 22 is formed a p-type emitter region 23. Also, the surface layer of the p-type collector region 21 is formed with a collector take-out part 24 separate from the n-type base region 22 and graft base 22a. The collector take-out part 24 contains a p-type impurity at a higher concentration than the p-type collector region 21.
On the n-type epitaxial layer 2 or LOCOS 3 is formed for example a silicon oxide film 9 as a first insulating film. In the silicon oxide film 9 on the base take-out part, p-type emitter region 23, and collector take-out part 24 are formed openings. At the opening on the p-type emitter region 23 is formed an emitter take-out electrode 25 comprised of p-type polysilicon. In the same way, at the opening on the collector take-out part 24 is formed a collector take-out electrode 26 comprised of p-type polysilicon. Electrodes 13 are formed on the base take-out part, emitter take-out electrode 25, and collector take-out electrode 26.
As shown in FIG. 3A, the S-pnp has a p-type collector region 21 in the n-type epitaxial layer 2. A part of the p-type collector region 21 reaches the surface of the p-type semiconductor substrate 1. Also, in the n-type epitaxial layer 2 are formed an n-type base region 22 and a graft base 22a. A part of the n-type base region 22 is formed on the p-type collector region 21. At the surface layer of the n-type base region 22 on the p-type collector region 21 is formed a p-type emitter region 23. Also, at the surface layer of the p-type collector region 21 is formed a collector take-out part 24. The collector take-out part 24 contains a p-type impurity at a higher concentration than the p-type collector region 21.
On the n-type epitaxial layer 2 or LOCOS 3 is formed for example a silicon oxide film 9 as a first insulating film. In the same way as the V-pnp shown in FIG. 2B, the silicon oxide film 9 on the base take-out part, p-type emitter region 23, and collector take-out part 24 are provided with openings. At the opening on the p-type emitter region 23 is formed an emitter take-out electrode 25 comprised of p-type polysilicon. In the same way, at the opening on the collector take-out part 24 is formed a collector take-out electrode 26 comprised of p-type polysilicon. Electrodes 13 are formed on the base take-out part, emitter take-out electrode 25, and collector take-out electrode 26.
As shown in FIG. 3B, the MIS-C has in the n-type epitaxial layer 2 a lower electrode layer 27 wherein an n-type impurity is diffused. On the n-type epitaxial layer 2 or LOCOS 3 is formed for example a silicon oxide film 9 as a first insulating film. In an opening formed in the silicon oxide film 9 on the lower electrode layer 27 and on the silicon oxide film 9 around the opening is formed a capacitor dielectric layer 28 comprised of for example a silicon nitride film.
On the capacitor dielectric layer 28 is formed an upper electrode 29 comprised of a p-type polysilicon layer. The upper electrode 29 is covered with a silicon oxide film 11 comprised of a second insulating film. The silicon oxide film 11 on the upper electrode 29 is formed with an opening. In the opening are formed an interconnection connected to the upper electrode 29. Also, the interconnection 30 connected to the lower electrode layer 27 is formed on the lower electrode layer 27 except for a part where the capacitor dielectric layer 28 and upper electrode 29 are formed.
As shown in FIG. 4, the Poly-R has a polysilicon resistor layer 31 on the LOCOS 3 via the silicon oxide film 9. The polysilicon resistor layer 31 contains an n-type impurity, and the polysilicon resistor layer 31 is covered with the silicon oxide film 11. In the silicon oxide film 11 on the polysilicon resistor layer 31 is formed an interconnection 30 connected to the polysilicon resistor layer 31.
In the above elements shown in FIGS. 1 to 4, on each layer comprised of polysilicon (the p-type base electrode 10 of FIG. 1, the emitter take-out electrode 18 and collector take-out electrode 19 of FIG. 2A, the emitter take-out electrode 25 and collector take-out electrode 26 of FIGS. 2B and 3A, the upper electrode 29 of FIG. 3B, and the polysilicon resistor layer 31 of FIG. 4) is formed a silicon oxide film 11.
As these silicon oxide film 11, a non-doped silicon oxide film (NSG; non-doped silicate glass) formed by chemical vapor deposition (CVD) is usually used. When NSG is used as the silicon oxide film 11, autodoping does not occur. Therefore, for example, when the NSG film is used as the silicon oxide film 11 in the V-npn shown in FIG. 1, it becomes possible to stabilize a base/emitter junction and form a shallow junction.
Also, each element shown in FIGS. 2 to 4 has a structure suitable for mixed mounting on the same substrate with the V-npn of a double polysilicon structure shown in FIG. 1. For example, a polysilicon layer and a silicon oxide film on it etc. can be formed by the same process between the elements.
In the elements shown in FIGS. 1 to 4, for the purpose of miniaturization of elements, all of the processing of the polysilicon layer or insulating film is conducted by reactive ion etching. (RIE). During the RIE, damage due to RIE is given to the surface of the semiconductor substrate or thermal oxide film and CVD insulating film to which reaction products of RIE stick.
Also, in photolithography for RIE, when unnecessary resist is removed, it is difficult to completely remove the resist residue strongly adhering to the semiconductor substrate or thermal oxide film and CVD insulating film.
These reaction products and strongly adhering resist residue diffuse or damage elements without diffusion due to heat treatment etc. in the production process. The extremely small amounts of mobile ions contained in the reaction products makes the surface conditions unstable and reduces the transistor characteristics. For example, in a reliability test of a junction of a bipolar transistor, the current amplification factor hFE decreases. Here, the reliability test of a junction is a test in which a certain amount of reverse bias is applied to the junction at a high temperature for a long time and deterioration is monitored.
Also, in capacitors and resistors, the presence of mobile ions makes the capacitance characteristics and resistance unstable.